Kevin K. Chan
227Patents
27h-index
252Co-inventors
93Inventor score
Filing activity: May 13, 1987 → Nov 5, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6057212A | Method for making bonded metal back-plane substrates | Electricity | 338 | Expired |
| US6444592B1 | Interfacial oxidation process for high-k gate dielectric process integration | Electricity | 137 | Expired |
| US6096590A | Scalable MOS field effect transistor | Electricity | 134 | Expired |
| US7071103B2 | Chemical treatment to retard diffusion in a semiconductor overlayer | Electricity | 120 | Expired |
| US6891227B2 | Self-aligned nanotube field effect transistor and method of fabricating same | Emerging Cross-Sectional Technologies | 113 | Expired |
| US6660598B2 | Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region | Electricity | 97 | Expired |
| US6365465B1 | Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques | Electricity | 94 | Expired |
| US7087965B2 | Strained silicon CMOS on hybrid crystal orientations | Electricity | 84 | Expired |
| US8043920B2 | finFETS and methods of making same | Electricity | 82 | Active |
| US6645861B2 | Self-aligned silicide process for silicon sidewall source and drain contacts | Electricity | 61 | Expired |
| US6841831B2 | Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process | Electricity | 57 | Expired |
| US7595010B2 | Method for producing a doped nitride film, doped oxide film and other doped films | Electricity | 54 | Active |
| US8288758B2 | SOI SiGe-base lateral bipolar junction transistor | Electricity | 53 | Active |
| US7361611B2 | Doped nitride film, doped oxide film and other doped films | Electricity | 51 | Expired |
| US7705345B2 | High performance strained silicon FinFETs device and method for forming same | Electricity | 46 | Expired |
| US6503833B1 | Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby | Electricity | 40 | Expired |
| US6580132B1 | Damascene double-gate FET | Electricity | 39 | Expired |
| US8420493B2 | SOI SiGe-base lateral bipolar junction transistor | Electricity | 39 | Active |
| US6809005B2 | Method to fill deep trench structures with void-free polysilicon or silicon | Electricity | 38 | Expired |
| US5133986A | Plasma enhanced chemical vapor processing system using hollow cathode effect | Emerging Cross-Sectional Technologies | 38 | Expired |
| US4978421A | Monolithic silicon membrane device fabrication process | Emerging Cross-Sectional Technologies | 36 | Expired |
| US6838695B2 | CMOS device structure with improved PFET gate electrode | Electricity | 33 | Expired |
| US7955928B2 | Structure and method of fabricating FinFET | Electricity | 31 | Active |
| US6236060A | Light emitting structures in back-end of line silicon technology | Electricity | 30 | Expired |
| US6448131B1 | Method for increasing the capacitance of a trench capacitor | Emerging Cross-Sectional Technologies | 28 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.