Masking method used in salicide process for improved yield by preventing damage to oxide spacers
US5451546A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 1994 |
| Grant date | Sep 19, 1995 |
| Priority date | — |
| Expiry date | Mar 10, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76889
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A masking method for use in a silicide formation process is disclosed herein which prevents an oxide etching solution from tunneling under a photoresist masking layer and damaging oxide spacers not intended to be etched. This process may be used during the formation of a bipolar or MOS transistor formed in an isolated silicon island. A mask opening used to etch exposed oxide spacer portions is made to not expose any parasitic oxide spacers formed along an edge of the isolated silicon island. In this way, an oxide etch solution is prevented from tunneling along the parasitic oxide spacer and reaching any intersecting oxide spacers not intended to be etched. The desired oxide spacers will thus be intact to properly isolate silicide portions formed over exposed silicon and polysilicon surfaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.