Structure and method of making a capacitor for an intergrated circuit
US5452178A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Apr 7, 1994 |
| Grant date | Sep 19, 1995 |
| Priority date | — |
| Expiry date | Apr 7, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
Abstract
A capacitor structure for a memory element of an integrated circuit is provided. The capacitor is formed within a via hole defined through a first dielectric layer, and comprises a bottom electrode defined by an underlying conductive layer, and a capacitor dielectric filling the via with a dielectric barrier layer lining the via and separating the capacitor dielectric from the first dielectric layer. The capacitor dielectric is characterized by a material with high dielectric strength, preferably a ferroelectric material. An overlying conductive layer defines a top electrode contacting the capacitor dielectric. The barrier layer may comprise dielectric sidewall spacer formed within the via, or alternatively may comprise a region of mixed composition formed by interdiffusion of the first dielectric layer and the capacitor dielectric. The resulting capacitor structure is simple and compact, and may be fabricated with known CMOS, Bipolar or Bipolar-CMOS processes for submicron VLSI and ULSI integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.