Hierarchically connected reconfigurable logic assembly
US5452231A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 1994 |
| Grant date | Sep 19, 1995 |
| Priority date | — |
| Expiry date | May 17, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of electronically reconfigurable gate array (ERCGA) logic circuits are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected circuits. The reconfigurable interconnect permits the digital network realized on the interconnected circuits to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA circuits dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic circuits. Other reconfigurable interconnect topologies are also detailed. If desired, the logic circuits and interconnect can be implemented in wafer-scale technology. Hybrid simulation employing both an ERCGA hardware simulator and a second simulator permits intermediate states of a circuit's operation to be reached quickly and analyzed in detail.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.