Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system
US5452239A · kind A · utility
312Cited by
4References
2Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 26, 1993 |
| Grant date | Sep 19, 1995 |
| Priority date | — |
| Expiry date | Feb 26, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An emulation system and method that reduces or eliminates the number of timing errors such as hold time violations when implementing a netlist description of an integrated circuit. The emulation system comprises a plurality of reprogrammable logic circuits and a plurality of reprogrammable interconnect circuits. The netlist description is optimized to reduce the number of timing violations by removing the occurences of gated clocks from the netlist, partitioning the netlist description by taking into account the occurence of timing violations and ensuring that retain state nets are implemented properly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.