Coordinating speculative and committed state register source data and immediate source data in a processor
US5452426A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 1994 |
| Grant date | Sep 19, 1995 |
| Priority date | — |
| Expiry date | Jan 4, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism for coordinating source data in a processor, wherein a decode circuit issues instructions comprising at least one immediate valid flag and at least one logical register source. The immediate valid flag indicates whether an immediate operand for the instruction is available on an immediate data bus, and the logical register source specifies a physical register or a committed state register. A speculative result data value and a speculative source valid flag are read from the physical register, and a committed result data value is read from the committed state register. The speculative result data value and the speculative source valid flag or the committed result data value and the committed source valid flag provide a source data value and a source data valid flag for scheduling an execution of the instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.