Method of making an EEPROM
US5453388A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 1993 |
| Grant date | Sep 26, 1995 |
| Priority date | — |
| Expiry date | Oct 7, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
Disclosed is a flash EEPROM cell needing only a 5 volt external source using an on-chip voltage multiplier circuit to provide high voltages necessary to effect Fowler-Nordheim tunneling during both the program and erase modes. Properties of dielectric layers between a floating gate and a control gate and between the floating gate and a drain region differ to facilitate programming and erasing of the floating gate. Also disclosed is a method for producing a flash EEPROM cell by forming the insulative layer between a floating gate and a control gate to have a capacitance lower than the capacitance of the insulating layer between the floating gate and a drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.