BiCMOS Static RAM with active-low word line
US5453949A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1994 |
| Grant date | Sep 26, 1995 |
| Priority date | — |
| Expiry date | Aug 31, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static RAM memory is ideally suited for BiCMOS processes. As in standard CMOS memory cells, the cells have cross-coupled inverters that have more efficient n-channel transistors for the drive transistors, which pull a bit line low during a read operation. The weaker p-channel transistors are used for load transistors in the cross-coupled inverters, adding to cell stability while requiring no power. In contrast to prior-art cells, p-channel pass transistors are used. Common-emitter word-line drivers are also used that require a small input-voltage swing in comparison with the large word-line voltage swing. A low voltage on the word line selects a memory cell by causing p-channel pass transistors to conduct, coupling bit lines to the cross-coupled inverters in the memory cell. Power consumption is reduced since only one selected word line is at a low voltage, while the deselected word lines are at a high voltage. Common-emitter word-line drivers have a conduction path from the positive supply terminal to ground when the output word line is low, but no conduction path when the output word line is high. Thus only the common-emitter word-line driver that is connected to the selected l…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.