Through hole interconnect substrate fabrication process
US5454161A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 1993 |
| Grant date | Oct 3, 1995 |
| Priority date | — |
| Expiry date | Apr 29, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high density through-hole interconnect with high aspect ratio vias is formed by sequentially forming layers of dielectric material on a previous dielectric layer. After each layer is formed, a plurality of through holes are etched through each layer and filled or metalized with an electrically conductive material having a coefficient of thermal expansion matching that of the dielectric layers and the integrated circuit that it will connect with. Preferably, the process of forming dielectric layers, forming through holes, and metalizing the through holes is repeated until the metalized through holes have an aspect ratio in the range of from 6 to 10. A support structure is constructed to interconnect with and support the metalized vias while the dielectric material is removed. A second dielectric material having the desired mechanical and electrical properties is poured into the support structure to fill the space between the metalized vias and allowed to solidify. The support structure is removed and the through-hole interconnector, comprising the metalized vias and the second dielectric material, is lapped and polished to predetermined manufacturing dimensions and tolerances.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.