CMOS buffer circuit with controlled current source

US5455527A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Brian Murphy · San Jose, US
• Martin Zibert · Feldkirchen-Westerham, DE

Key dates

• Filing date: Sep 17, 1993
• Grant date: Oct 3, 1995
• Expiry date: Sep 17, 2013

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K19/01855
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

An integrated buffer circuit configuration has two inverters which are mutually connected in series. A circuit node lies between the two inverters. At least the first inverter is a CMOS inverter for an input signal IN. The CMOS inverter has an n-channel transistor which is connected to a first supply potential. The source of a p-channel transistor is connected with a constant current source. A first enable transistor is connected between the n-channel transistor of the first inverter and the circuit node. A second enable transistor is connected in parallel to the configuration formed by the constant current source and the p-channel transistor of the first inverter. The gates of the enable transistors are connected with the enable input of the buffer circuit. An enable signal present at the enable input makes it possible to deactivate the buffer circuit in the case of disturbances with a known course over time. A MOS-transistor may function as the constant current source. The MOS-transistor is then connected to a second supply potential and its gate lies at reference potential with a value with always has a constant difference with respect to the second supply potential. During oper…