Circuit having a control array of memory cells and a current source and a method for generating a self-refresh timing signal
US5455801A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 1994 |
| Grant date | Oct 3, 1995 |
| Priority date | — |
| Expiry date | Jul 15, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0231
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit for generating a self-refresh mode signal and a self-refresh cycle signal. The circuit is a dynamic random access memory (DRAM) device having a control array of control cells charged to a potential by a current source and having a monitor circuit for monitoring the potential of the control array. The DRAM comprises a discharge circuit which discharges the potential of the control array in response to the monitor circuit detecting when the potential of the control array has reached a trip point. A counter circuit counts the number of cycles of charge and discharge and generates the self-refresh mode signal after a desired count is reached. The counter circuit continues to count the number of cycles of charge and discharge while in the refresh mode and generates a self-refresh cycle signal each time the counter circuit counts a desired number of counts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.