Programmable clock tuning system and method
US5455931A · kind A · utility
37Cited by
7References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 19, 1993 |
| Grant date | Oct 3, 1995 |
| Priority date | — |
| Expiry date | Nov 19, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock tuning system and method for a data processing system with enhanced timing failure diagnostics and unlayering capabilities. Both common and individual phase adjusting capabilities ensure programmable tuning of clock pulses distributed throughout a computer system, thereby facilitating isolation of timing margin failure to specific clock signals or enhancing system performance by shifting timing margin between logic paths. Both single-clock and dual-clock data processing are discussed, as well as clock tuning embodiments for each.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.