Peter J. Camporese
13Patents
9h-index
19Co-inventors
61Inventor score
Filing activity: Nov 19, 1993 → Jun 29, 2001
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6311313A | X-Y grid tree clock distribution network with tunable tree and grid networks | Physics | 124 | Expired |
| US6205571A | X-Y grid tree tuning method | Physics | 62 | Expired |
| US6487706B1 | Contract methodology for concurrent hierarchical design | Physics | 38 | Expired |
| US5455931A | Programmable clock tuning system and method | Physics | 37 | Expired |
| US6629298B1 | Automated programmable process and method for the improvement of electrical digital signal transition rates in a VLSI design | Physics | 16 | Expired |
| US6546529B1 | Method for performing coupling analysis | Physics | 14 | Expired |
| US6323050A | Method for evaluating decoupling capacitor placement for VLSI chips | Physics | 11 | Expired |
| US6374394B1 | Method to identify unit pins that are not optimally positioned in a hierarchically designed VLSI chip | Physics | 10 | Expired |
| US6460169B1 | Routing program method for positioning unit pins in a hierarchically designed VLSI chip | Physics | 9 | Expired |
| US6415428B1 | Minimal length method for positioning unit pins in a hierarchically designed VLSI chip | Physics | 7 | Expired |
| US6618843B2 | Method for evaluating decoupling capacitor placement for VLSI chips | Physics | 5 | Expired |
| US6618844B2 | Method for evaluating decoupling capacitor placement for VLSI chips | Physics | 4 | Expired |
| US6341365B1 | Method for automating the placement of a repeater device in an optimal location, considering pre-defined blockages, in high frequency very large scale integration/ultra large scale integration (VLSI/ULSI) electronic designs | Physics | 2 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.