Architecture of a multiple array high density programmable logic device with a plurality of programmable switch matrices
US5457409A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 1992 |
| Grant date | Oct 10, 1995 |
| Priority date | — |
| Expiry date | Aug 3, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17792
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The programmable logic device (PLD) of this invention includes two or more programmable logic blocks interconnected by a programmable switch matrix that includes a programmable input switch matrix (input switch matrix) and a programmable centralized switch matrix (centralized switch matrix). Each programmable logic block receives input signals only from the centralized switch matrix. The output signals from a programmable logic block are coupled to a plurality of input/output (I/O) pins by an output switch matrix. The output signals from the programmable logic block are also fed directly to the programmable input switch matrix. In addition, an input macrocell couples the signal on an I/O pin driving the input macrocell, i.e., the associated I/O pin, to the programmable input switch matrix. Each programmable logic block includes a programmable logic array, a programmable logic allocator, and programmable logic macrocells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.