Edge selective delay circuit
US5459422A · kind A · utility
22Cited by
9References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 2, 1993 |
| Grant date | Oct 17, 1995 |
| Priority date | — |
| Expiry date | Jun 2, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/131
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital circuit for independently controlling the delay of the falling edge and the delay of the rising edge of a digital signal which consist of two serially connected circuits which contain identical synchronous delay lines connected to a logical switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.