System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory
US5459842A · kind A · utility
126Cited by
7References
17Claims
0Family size
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Key dates
| Filing date | Jun 26, 1992 |
| Grant date | Oct 17, 1995 |
| Priority date | — |
| Expiry date | Jun 26, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1631
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A write compression buffer is connected to a CPU bus and to a memory controller to provide write cycle compression in which plural partial write requests to the same memory address are compressed into a single memory write cycle. The buffer has a plurality of buffering level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.