Substrate for tensilely strained semiconductor
US5461243A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1993 |
| Grant date | Oct 24, 1995 |
| Priority date | — |
| Expiry date | Oct 29, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02502
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure with strained and defect free semiconductor layers. In a preferred embodiment, silicon on insulator may be used as a substrate for the growth of fully relaxed SiGe buffer layers. A new strain relief mechanism operates, whereby the SiGe layer relaxes without the generation of threading dislocations within the SiGe layer. This is achieved by depositing SiGe on an SOI substrate with a superficial silicon thickness. Initially the strain in the SiGe layer becomes equalized with the thin Si layer by creating tensile strain in the Si layer. Then the strain created in the thin Si layer is relaxed by plastic deformation during an anneal. Since dislocations are formed, and glide in the thin Si layer, threading dislocations are not introduced into the upper SiGe material. A strained silicon layer for heterostructures may then be formed on the SiGe material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.