Multi-layered lead frame assembly for integrated circuits
US5461255A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 1994 |
| Grant date | Oct 24, 1995 |
| Priority date | — |
| Expiry date | Jan 14, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is provided a packaged semiconductor device having a multi-layered lead frame assembly (38). An integrated circuit chip (12) has an active face (16) with a plurality of bond pads (18) disposed along its center line (14). A first pair of insulating adhesive tape strips (20) adhere a main lead frame (22) to the active face (16) of chip (12). A second pair of insulating adhesive tape strips (28) adhere a respective pair of bus lead frames (30) to the main lead frame (24). Welds (36) electrically interconnect selective leads (22) of main lead frame (22) with respective leads (32) of bus lead frames (30). Tab bonds (40) or wire bonds (42) electrically interconnect selective leads (24) of main lead frame (22) with bond pads (18) on chip (12).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.