Method of fabricating defect-free silicon on an insulating substrate
US5462883A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 1994 |
| Grant date | Oct 31, 1995 |
| Priority date | — |
| Expiry date | Apr 11, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating silicon on insulator structures having a dislocation free silicon layer. The method utilizes low temperature UHVCVD to deposit a very heavily doped etch stop layer having a very steep doping profile onto a substrate and a lightly doped active layer onto the etch stop layer. An insulator is formed on the active layer and a carrier wafer is formed on the insulator layer. The original substrate is removed in a first etch and the etch stop layer is removed in a second etch resulting in a thin, uniform active layer. In one embodiment, a small percentage of germanium is added to the etch stop layer to produce a defect free epitaxial active layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.