Method of forming a sidewall on a semiconductor element
US5462896A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 1992 |
| Grant date | Oct 31, 1995 |
| Priority date | — |
| Expiry date | Jun 23, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method fabricates a semiconductor device having a sidewall made from an insulation film at each side of a gate electrode portion. The method forms a polysilicon gate electrode (11a) on a gate oxide film (10) in a predetermined region on an n.sup.- epitaxial layer (2). A CVD silicon oxide film (15) having a predetermined thickness is formed over the polysilicon gate electrode material (11a) on the n.sup.- epitaxial layer (2). A magnetron enhanced reactive ion etching apparatus is used to etch the CVD silicon oxide film (15) while pouring a CHF.sub.3 gas made by coupling carbon, hydrogen, and fluorine and an N.sub.2 gas onto the etched material, such that the CVD silicon oxide film (15) is left only at each side of the polysilicon gate electrode material (11a), to form a sidewall (16). To avoid electrodes of the magnetron enhanced reactive ion etching apparatus from staining, CHF.sub.3 /He/N.sub.2 /O.sub.2 may be used for etching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.