CMOS structure with parasitic channel prevention
US5463238A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 1993 |
| Grant date | Oct 31, 1995 |
| Priority date | — |
| Expiry date | Feb 25, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6744
Abstract
A semiconductor device comprises a complementary MOS transistor integrated circuit formed in a semiconductor single crystal silicon disposed on an electrically insulating layer. A thickness of the single crystal silicon in a region in which an N-type MOS transistor is formed is made thicker than the thickness in a region in which a P-type MOS transistor is formed. By this structure, the bottoms of the source region and the drain region of the N-type transistor are separated from the electrically insulating layer by a predetermined distance. The separation of the source region and the drain region from the electrically insulating layer is effective to prevent a parasitic channel from forming, thereby reducing leakage current and making the semiconductor device more efficient.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.