Redundant memory channel array configuration with data striping and error correction capabilities
US5463643A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 1994 |
| Grant date | Oct 31, 1995 |
| Priority date | — |
| Expiry date | Mar 7, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory channel array configuration wherein two or more memory channels are used for data transfer and data is striped across each of the memory channels. In addition, one or more redundant memory channels, preferably a single dedicated parity channel, are used for error correction. In the preferred embodiment the memory channel configuration utilizes RAMBUS based memory channels, and thus the present invention provides error correction for a RAMBUS based memory system. Also, the use of multiple memory channels in conjunction with data striping across each of the channels allows for much higher data transfer bandwidths than is available using prior art implementations of RAMBUS technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.