Methods and apparatus for determining the next instruction pointer in an out-of-order execution computer system
US5463745A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1993 |
| Grant date | Oct 31, 1995 |
| Priority date | — |
| Expiry date | Dec 22, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Instructions are fetched and issued by an instruction fetch and issue circuit with the instructions' sizes in program order. An allocate circuit allocates reservation station entries in a reservation station circuit, and reorder buffer entries in a reorder circuit, for the issued instructions in order, storing the instructions' sizes in the allocated reorder buffer entries. The reservation and dispatch circuit dispatches the issued instructions to the execution circuits for execution when they are ready. The execution circuits store the result data including target addresses of branch instructions into the corresponding reorder buffer entries. During each retirement operation, a retire circuit reads the instruction sizes and the target addresses for a predetermined number of issued instructions from their allocated reorder buffer entries. The retire circuit determines two or more speculative next instruction pointers for each of the issued instructions, factoring into consideration whether the issued instructions are branch instructions or not, and their relative positions to each other. Each of the speculative next instruction pointers indicates what the next instruction pointer f…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.