Darrell D. Boggs
50Patents
22h-index
66Co-inventors
91Inventor score
Filing activity: Dec 22, 1993 → Jun 28, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6799268B1 | Branch ordering buffer | Physics | 129 | Expired |
| US6385715B1 | Multi-threading for a processor utilizing a replay queue | Physics | 84 | Expired |
| US6889319B1 | Method and apparatus for entering and exiting multiple threads within a multithreaded processor | Physics | 84 | Expired |
| US6496925B1 | Method and apparatus for processing an event occurrence within a multithreaded processor | Physics | 83 | Expired |
| US6041403A | Method and apparatus for generating a microinstruction responsive to the specification of an operand, in addition to a microinstruction based on the opcode, of a macroinstruction | Physics | 78 | Expired |
| US6981129B1 | Breaking replay dependency loops in a processor using a rescheduled replay queue | Physics | 72 | Expired |
| US5463745A | Methods and apparatus for determining the next instruction pointer in an out-of-order execution computer system | Physics | 54 | Expired |
| US6163838A | Computer processor with a replay system | Physics | 52 | Expired |
| US7051329B1 | Method and apparatus for managing resources in a multithreaded processor | Physics | 51 | Expired |
| US6633970B1 | Processor with registers storing committed/speculative data and a RAT state history recovery mechanism with retire pointer | Physics | 49 | Expired |
| US5687338A | Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor | Physics | 49 | Expired |
| US5625788A | Microprocessor with novel instruction for signaling event occurrence and for providing event handling information in response thereto | Physics | 43 | Expired |
| US7039794B2 | Method and apparatus for processing an event occurrence for a least one thread within a multithreaded processor | Physics | 42 | Expired |
| US5566298A | Method for state recovery during assist and restart in a decoder having an alias mechanism | Physics | 40 | Expired |
| US7200737B1 | Processor with a replay system that includes a replay queue for improved throughput | Physics | 37 | Expired |
| US7181598B2 | Prediction of load-store dependencies in a processing agent | Physics | 30 | Expired |
| US6877086B1 | Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter | Physics | 30 | Expired |
| US6094717A | Computer processor with a replay system having a plurality of checkers | Physics | 27 | Expired |
| US6735688B1 | Processor having replay architecture with fast and slow replay paths | Physics | 26 | Expired |
| US5537560A | Method and apparatus for conditionally generating a microinstruction that selects one of two values based upon control states of a microprocessor | Physics | 26 | Expired |
| US6651158B2 | Determination of approaching instruction starvation of threads based on a plurality of conditions | Physics | 25 | Expired |
| US5974523A | Mechanism for efficiently overlapping multiple operand types in a microprocessor | Physics | 24 | Expired |
| US6779103B1 | Control word register renaming | Physics | 22 | Expired |
| US10642744B2 | Memory type which is cacheable yet inaccessible by speculative instructions | Physics | 21 | Active |
| US9875105B2 | Checkpointed buffer for re-entry from runahead | Physics | 20 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.