Insulated gate bipolar transistor provided with a minority carrier extracting layer
US5464992A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1994 |
| Grant date | Nov 7, 1995 |
| Priority date | — |
| Expiry date | Dec 19, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/393
Abstract
A p type pad well layer is formed at the surface of an n.sup.- type drain layer under a gate bonding pad and the surface thereof is provided with a p.sup.++ type pad layer to be provided with lower resistivity. The p.sup.++ type pad layer is connected with a source electrode through a contact hole. Since the gate electrode supplying each cell with gate potential is of a pattern having extensions in a comb-teeth form arranged along the boundary between the pad region and the cell region, there is present substantially no gate electrode under the pad. Hence, introduction of impurities into the entire surface of the well layer under the pad region can be performed simultaneously with formation of p.sup.++ type contact layers after the formation of the gate electrode, and accordingly, the low resistance p.sup.++ type pad layer can be easily formed. The p.sup.++ type pad layer serves as a low resistance path for allowing the holes flowing into the region under the pad region of the insulated gate bipolar transistor to escape to the source electrode, whereby occurrence of the latch up and increase in the turn-off time due to the minority carriers concentrating into the border portion cel…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.