Planarized local oxidation by trench-around technology
US5465003A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 1994 |
| Grant date | Nov 7, 1995 |
| Priority date | — |
| Expiry date | Dec 1, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76232
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A new planarized device isolation structure within a semiconductor substrate is described. The device isolation structure comprises narrow device isolation regions each consisting of a deep trench having a thin oxide covering its sidewalls and bottom and filled with silicon oxide, wide device isolation regions each consisting of two deep trenches flanking a shallow trench wherein each deep trench has a thin oxide covering its sidewalls and bottom and is filled with silicon oxide and wherein the shallow trench is filled with a field oxide. The top surface of the narrow and wide device isolation regions and the semiconductor substrate is planarized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.