RAM-logic tile for field programmable gate arrays
US5465055A · kind A · utility
9Cited by
28References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 19, 1994 |
| Grant date | Nov 7, 1995 |
| Priority date | — |
| Expiry date | Oct 19, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved RAM-logic tile (RLT) for use in a field programmable gate array (FPGA) is presented. The RLTs are located at the intersection of global horizontal and vertical lines. Wiring segments run locally between RLTs and contain programmable antifuses for connecting segments within an RLT and to neighboring RLTs. The RLTs are implemented with transmission gates and can be efficiently configured into a memory structure and/or logic device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.