Michael G. Ahrens
24Patents
10h-index
21Co-inventors
75Inventor score
Filing activity: Sep 23, 1988 → Apr 29, 2009
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5221865A | Programmable input/output buffer circuit with test capability | Electricity | 103 | Expired |
| US5534798A | Multiplexer with level shift capabilities | Electricity | 60 | Expired |
| US6212103A | Method for operating flash memory | Electricity | 48 | Expired |
| US5286992A | Low voltage device in a high voltage substrate | Emerging Cross-Sectional Technologies | 27 | Expired |
| US4918341A | High speed static single-ended sense amplifier | Electricity | 26 | Expired |
| US6233177A | Bitline latch switching circuit for floating gate memory device requiring zero volt programming voltage | Physics | 22 | Expired |
| US5671234A | Programmable input/output buffer circuit with test capability | Electricity | 20 | Expired |
| US5299150A | Circuit for preventing false programming of anti-fuse elements | Electricity | 20 | Expired |
| US6249458A | Switching circuit for transference of multiple negative voltages | Physics | 19 | Expired |
| US5453696A | Embedded fuse resistance measuring circuit | Physics | 13 | Expired |
| US5465055A | RAM-logic tile for field programmable gate arrays | Electricity | 9 | Expired |
| US6687157B1 | Circuits and methods for identifying a defective memory cell via first, second and third wordline voltages | Physics | 7 | Expired |
| US6525973B1 | Automatic bitline-latch loading for flash prom test | Physics | 6 | Expired |
| US5652527A | Input-output circuit for increasing immunity to voltage spikes | Electricity | 5 | Expired |
| US7544968B1 | Non-volatile memory cell with charge storage element and method of programming | Electricity | 5 | Expired |
| US6285584A | Method to implement flash memory | Electricity | 5 | Expired |
| US5629636A | Ram-logic tile for field programmable gate arrays | Electricity | 4 | Expired |
| US7420842B1 | Method of programming a three-terminal non-volatile memory element using source-drain bias | Physics | 4 | Expired |
| US7450431B1 | PMOS three-terminal non-volatile memory element and method of programming | Physics | 3 | Expired |
| US6112322A | Circuit and method for stress testing EEPROMS | Physics | 3 | Expired |
| US6388946B1 | Circuit and method for incrementally selecting word lines | Physics | 3 | Expired |
| US6272060A | Shift register clock scheme | Physics | 2 | Expired |
| US7687797B1 | Three-terminal non-volatile memory element with hybrid gate dielectric | Electricity | 0 | Expired |
| US7947980B1 | Non-volatile memory cell with charge storage element and method of programming | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.