Reset generation circuit to reset self resetting CMOS circuits
US5467037A · kind A · utility
28Cited by
14References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 21, 1994 |
| Grant date | Nov 14, 1995 |
| Priority date | — |
| Expiry date | Nov 21, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356008
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A self resetting CMOS (SRCMOS) circuit operates with a variable clock cycle. Circuit oscillation is avoided in either long or short clock cycles. At the same time, the circuit eliminates overlapping currents by incorporating a ground interrupt device. The reset generation path is optimized to provide a fast and narrow reset pulse. In addition, the circuit saves power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.