Semiconductor memory device
US5467302A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 1994 |
| Grant date | Nov 14, 1995 |
| Priority date | — |
| Expiry date | Dec 12, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Bit lines BL0 and /BL0 are connected to a sense amplifier SA0, the gate of a first MOS transistor to a first word line WL0, a first electrode of a first ferrodielectric capacitor Cs1 to the source of the first Qn, the drain of the first Qn to BL0, a second electrode of Cs1 to a first plate electrode CP0, the gate of a second MOS transistor Qn to a second word line DWL0, a first electrode of a second ferrodielectric capacitor Cd2 to the source of the second Qn, the drain of the second Qn to /BL0, and a second electrode of Cd1 to a second plate electrode DCP0, and after turning off the second Qn, the logic voltage of DCP0 is inverted. Hence, in a semiconductor memory device employing the ferrodielectric element, the dummy memory capacitor is initialized securely, and high speed reading is enabled without concentration of power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.