Adaptive clock skew and duty cycle compensation for a serial data bus
US5467464A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 1993 |
| Grant date | Nov 14, 1995 |
| Priority date | — |
| Expiry date | Mar 9, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/044
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The de-skewer utilizes a delay line to generate a set of delayed versions of an input clock signal. A bank of flip-flops compares pulses within the delayed clock signals to a synchronization pulse provided within an input data signal. A detector receives outputs from the flip-flops and selects the delayed clock signal having the least amount of skew based on the values of the output from the flip-flops. A multiplexer outputs the selected delayed clock. The de-skewer provides a simple, open-loop circuit for eliminating skew between parallel transmission paths. The de-skewer is ideally suited for eliminating skew from sources which do not vary significantly as a function of time. In particular, the de-skewer is well-suited for use in a data transmission system providing short bursts of high data rate transmissions. A double-edged de-skewer is also described which is capable of generating a pair of clock signals for use in eliminating duty cycle distortion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.