Reduction of base-collector junction parasitic capacitance of heterojunction bipolar transistors
US5468659A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 1994 |
| Grant date | Nov 21, 1995 |
| Priority date | — |
| Expiry date | Mar 10, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/951
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A photoresist process combined with wet chemical etching and silicon oxide evaporation and self-aligned lift-off is used to reduce the parasitic (extrinsic) base-collector junction capacitance (C.sub.BC) of InP-based heterojunction bipolar transistors (HBTs). At least a portion of the mesa related to the base contact is etched around the intrinsic device area and then back-filled with evaporated oxide. The base contact pad is then formed over the back-filled oxide, thus reducing the extrinsic device area. This process provides a self-aligned etching of a mesa and deposition and lift-off of the back-fill oxide in one single photoresist processing step. The process is simple and reproducible and provides very high yield. It also eliminates the need for costly and complicated dry-etching techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.