Method of placing source contacts for efficient ESD/EOS protection in grounded substrate MOS integrated circuit
US5468667A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1994 |
| Grant date | Nov 21, 1995 |
| Priority date | — |
| Expiry date | Dec 15, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
An ESD/EOS protection circuit (100) for protecting an integrated circuit. A MOS transistor (102) is arranged in a multi-finger configuration having a plurality of drain regions (124), a plurality of source regions (122) and a plurality of gates (118). A first metal layer (162) substantially covers each of the drain regions (124) and is in contact with each of the drain regions (124) via drain contacts (130). A second metal layer (154) substantially covers each of the source regions (122) and is in contact with each of the source regions via source contacts (128). A plurality of source contacts (128) are located at a minimum distance from gates (118). Metal-to-metal contacts (160) connect a third metal layer (156) with the second metal layer (154) over each of the source regions (122).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.