Integrated circuit with layered superlattice material and method of fabricating same
US5468684A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | May 21, 1993 |
| Grant date | Nov 21, 1995 |
| Priority date | — |
| Expiry date | May 21, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N30/853
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A method of fabricating a ferroelectric or layered superlattice DRAM compatible with conventional silicon CMOS technology. A MOSFET is formed on a silicon substrate. A thick layer of BPSG followed by a thin SOG layer overlies the MOSFET. A capacitor is formed by depositing a layer of platinum, annealing, depositing an intermediate layer comprising a ferroelectric or layered superlattice material, annealing, depositing a second layer of platinum, then patterning the capacitor. Another SOG layer is deposited, contact holes to the MOSFET and capacitor are partially opened, the SOG is annealed, the contact holes are completely opened, and a Pt/Ti/PtSi wiring layer is deposited.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.