Semiconductor integrated circuit device having an improved vertical bipolar transistor structure

US5468989A · kind A · utility

Assignees

• HITACHI, LTD. · JP
• Hitachi VLSI Engineering Corp. · JP

Inventors

• Hirotaka Nishizawa · Fuchu, JP
• Seiichiro Azuma · Wenatchee, US
• Kazuaki Ootoshi · Wenatchee, US
• Masataka Miyama · Fuchu, JP
• Shuji Kawata · Wenatchee, US
• Osamu Kasahara · Toyama, JP
• Sinichi Suzuki · Wenatchee, US

Key dates

• Filing date: Oct 20, 1992
• Grant date: Nov 21, 1995
• Expiry date: Oct 20, 2012

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/126

Abstract

There is provided a semiconductor integrated circuit device having bipolar transistors each composed of an emitter region, base region, and collector region arranged vertically on a semiconductor substrate, said collector region having a plane figure, with the square corners thereof cut off. To be concrete, the buried collector region having a high concentration of impurity has its square corners cut off and the base region formed on the major surface of the epitaxial layer formed on said buried collector region has also its square corners cut off. The bipolar transistor having such a plane figure has a reduced parasitic capacity and an increased operating speed. A manufacturing method is also provided capable of producing a highly reliable groove isolation structure with a low dielectric constant.