Programmable logic device routing architecture
US5469078A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 6, 1994 |
| Grant date | Nov 21, 1995 |
| Priority date | — |
| Expiry date | Jan 6, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17704
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated electronic circuit architecture has low leakage current and capacitance and includes a user-programmable integrated circuit design (110) having a plurality of designed conductors (112, 118) and a plurality of designed functional circuit blocks (e.g., 12,14, etc.). In the architecture, a plurality of user-programmable antifuse elements (e.g., 26, 28, 30, etc.) connect to the plurality of conductors (112, 118) and the plurality of functional circuit blocks (12, 14, 16, etc.). The plurality of user-programmable antifuse elements (e.g., 26, 28, 30, etc.) connect the plurality of conductors (112, 118) with one another and to the plurality of functional circuit blocks (12, 14, 16, etc.). The plurality of conductors (112, 118) is segregated into at least two groups including a first group of conductors and a second group of conductors. Antifuses (26, 28, 32) in the first group of conductors are selectively depopulated to reduce capacitance and leakage associated with their placement in the user-programmable integrated circuit (110), while the conductors of the first group of conductors permit access to conductors in the second group of conductors. Segmentation transistors (1…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.