Circuit and method for decreasing the cell margin during a test mode
US5469393A · kind A · utility
66Cited by
4References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 15, 1993 |
| Grant date | Nov 21, 1995 |
| Priority date | — |
| Expiry date | Sep 15, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention is a monolithic memory device having a circuit and a method for decreasing the cell margin during a test mode. Decreasing the cell margin stresses the memory device during the test mode greater than a stress experienced during normal operation, thus test time can be decreased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.