Adaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor system
US5469555A · kind A · utility
101Cited by
27References
14Claims
0Family size
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Key dates
| Filing date | May 28, 1992 |
| Grant date | Nov 21, 1995 |
| Priority date | — |
| Expiry date | May 28, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for reducing the access time required to write to memory and read from memory in a computer system having a cache-based memory. A dynamic determination is made on a cycle by cycle basis of whether data should be written to the cache with a dirty bit asserted, or the data should be written to both the cache and main memory. The write-through method is chosen where the write-through method is approximately as fast as the write-back method. Where the write-back method is substantially faster than the write-through method, the write-back method is chosen.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.