Silicidation method for contactless EPROM related devices
US5470772A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 24, 1993 |
| Grant date | Nov 28, 1995 |
| Priority date | — |
| Expiry date | May 24, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/30
Abstract
A process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash contactless EPROM or EEPROM type. The array of memory cells in these devices have elongated, parallel source and drain regions disposed beneath field oxide regions. The word lines are elongated, parallel strips of polysilicon. A series of SiO.sub.2 depositions using TEOS chemistry in a PECVD process, and etches using sputter etch and plasma processes, is performed. After deposition and etchback, the polysilicon word lines remain exposed while all previous exposed substrate regions between source and drain are covered with SiO.sub.2. A metal deposition and silicidation are performed forming a silicide on the exposed silicon word lines thereby lowering the resistance of the word lines. Since the substrate regions between source and drain is covered between SiO.sub.2 prior to metal deposition and silicidation no silicide is formed in these regions. Therefore the word lines are silicidized in a self aligned process with no need for a photolithographic step after SiO.sub.2 deposition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.