Method for integrated circuit device isolation
US5470783A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 1995 |
| Grant date | Nov 28, 1995 |
| Priority date | — |
| Expiry date | Jan 9, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/05
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit fabrication process for creating field oxide regions in a substrate is disclosed. In the process, masking layers of oxide, nitride and deposited silicon dioxide are formed on the substrate. A pattern that defines the field oxide regions in the substrate is introduced into the substrate through these masking layers. The field oxide region is bordered by steep sidewalls in a portion of the substrate and the masking layers overlying the substrate. A thin layer of oxide is grown on the exposed portion of the substrate, and a conformal second layer of nitride followed by a conformal layer of a polycrystalline material are formed over the substrate/mask structure. The polycrystalline layer is selectively removed, so that the only portion of the polycrystalline material that remains on the structure is the portion covering the sidewalls. The exposed portions of the second nitride layer are then removed, leaving only those portions of the second nitride layer that are interposed between the polycrystalline material and the sidewalls on the substrate surface. The remaining portions of the polycrystalline material on the surface of the structure are then removed. The fi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.