Semiconductor device solder bump having intrinsic potential for forming an extended eutectic region and method for making and using the same
US5470787A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 2, 1994 |
| Grant date | Nov 28, 1995 |
| Priority date | — |
| Expiry date | May 2, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device (32) has an as-deposited solder bump (34) having the intrinsic potential for forming an extended eutectic region for simplified DCA applications. The as-deposited solder bump (34) has first tin layer (40) overlying the UBM of the bonding pad (14) on the device. The first tin layer reacts with a metal layer (36) in the UBM to form an intermetallic for adhering the solder bump to the bonding pad. A thick lead layer (42) overlies the first tin layer to provide the substantial component of the solder bump. A second tin layer (44) overlies the lead layer to provide localized eutectic formation at the top surface of the bump during reflow. A device having at least this solder bump structure can be directly attached to either ceramic or PC board substrates. Additional layers of tin and /or lead may be supplemented to the basic bump structure to optimize the eutectic formation rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.