Techniques for via formation and filling
US5471091A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1991 |
| Grant date | Nov 28, 1995 |
| Priority date | — |
| Expiry date | Aug 26, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/959
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Via filling is enhanced by the techniques of 1) providing pillars immediately underneath semiconductor features, such as metal layer contacts (inter-connection points), and 2) polishing off excess via-filling material so that the via-filling plug is flush with the topmost insulating layer. The pillars are provided under every feature over which a via will be formed, so that an insulating layer surrounding the via will be thinner at the location of the feature. If necessary, polishing is continued to thin the insulating layer so that the plugs in initially selectively under-filled vias are made flush with the insulating layer. Method and apparatus are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.