Fast static CMOS adder
US5471414A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 1993 |
| Grant date | Nov 28, 1995 |
| Priority date | — |
| Expiry date | Mar 17, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/507
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An N-bit conditional sum adder comprised of a number of 2-bit adders coupled in series. The 2-bit adders have a sum generation circuit which computes two sum bits from two 2-bit inputs. Each sum bit is processed by a maximum of two multiplexers in series for factoring any carry-ins from preceding 2-bit adders, regardless of the total number of N bits to be added. A carry generation circuit generates two carry signals. The appropriate carry signal is selected for propagation by a multiplexer comprised of a number of p-n passgates. The two carry signals plus their complements are first buffered before being input to the multiplexer. The multiplexer outputs the appropriate carry signal and its complement to be input to a succeeding 2-bit adder and for controlling a succeeding multiplexer selection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.