Bus master arbitration circuitry having improved prioritization
US5471590A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 1994 |
| Grant date | Nov 28, 1995 |
| Priority date | — |
| Expiry date | Jan 28, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arbiter which allows retried requests to have high priority in subsequent arbitrations by not changing priority on a granted, but aborted, access to the bus and yet prevents the aborted requestor from thrashing the bus by masking its bus request signal until the data is available. Further, should an access to main memory be retried, all bus requests except the one from the memory system are masked to provide the memory system the highest effective priority to allow any flushing operations to occur. The masking of the various bus requests allows the arbiter to control access to a PCI standard bus without requiring that specific signals be added. The arbiter further includes modified priority LRU techniques and provides a locking requestor with an additional, highest priority position if retried.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.