Nonvolatile memory process

US5474947A · kind A · utility

Assignee

• Motorola, Inc. · US

Inventors

• Ko-Min Chang · Austin, US
• Bruce L. Morton · Lakeway, US
• Henry Y. Choe · Austin, US
• Clinton C. K. Kuo · Austin, US

Key dates

• Filing date: Dec 27, 1993
• Grant date: Dec 12, 1995
• Expiry date: Dec 27, 2013

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/00

Abstract

A process for fabricating an improved nonvolatile memory device includes the formation of a control gate electrode (70) which overlies a floating gate electrode (42) and is separated therefrom by an inter-level-dielectric layer (62). The control gate electrode (70) and the underlying floating gate electrode (42) form a stacked gate structure (72) located in the active region (44) of a semiconductor substrate (40). An electrically insulating sidewall spacer (54) is formed at the edges of the floating gate electrode (42) and electrically isolates the control gate (70) from the semiconductor substrate (40). During the fabrication process, implanted memory regions (56, 58) are formed in the active region (44) prior to the formation of control gate electrode (70). A word-line (68) and the control gate (70) are formed by anisotropic etching of a semiconductor layer (66), which is deposited to overlie inter-level-dielectric layer (62). During the etching process, inter-level-dielectric layer (62) prevents the removal of surface portions of semiconductor substrate (40).