Test generation by environment emulation
US5475624A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 30, 1992 |
| Grant date | Dec 12, 1995 |
| Priority date | — |
| Expiry date | Apr 30, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3193
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Generation, validation and fault-grading of test patterns, and test and debug of logic circuits, are enhanced by emulation of the logic circuits in programmable gate arrays. Two emulations of the logic circuit are preferably created, one of which is a "good" model containing no faults and the other of which is a "faultable" model into which possible faults may be selectively introduced. A fault is introduced in the faultable model, and the two models are exercised in parallel by applying the same pattern of test vectors to both models. The test vector pattern may be generated by an emulation of the intended operating environment of the logic circuit. Differences in the output signals of the two models indicate that the fault has been detected by the applied test pattern. Application of the test pattern is repeated for each of a sequence of possible faults, to determine the extent to which the test pattern enables detection of faults in the logic circuit. A fault dictionary is produced which includes an indication of the test vector at which each fault is detected, the output signal differences indicative of fault detection, and a log of the faults detected. The faultable emulation …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.