Error management processes for flash EEPROM memory arrays
US5475693A · kind A · utility
149Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 1994 |
| Grant date | Dec 12, 1995 |
| Priority date | — |
| Expiry date | Dec 27, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of utilizing circuitry including error detecting and correcting circuitry to detect and correct errors which can occur in data stored in multi-bit per cell format in a flash EEPROM memory array before those errors can affect the accuracy of data provided by a flash EEPROM memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.