Built-in-self-test scheme for testing multiple memory elements
US5475815A · kind A · utility
27Cited by
33References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 11, 1994 |
| Grant date | Dec 12, 1995 |
| Priority date | — |
| Expiry date | Apr 11, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/56
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for efficiently testing a plurality of memory devices at the board level. The logic for the present invention is minimal and can be placed on a controller chip within the board design. In addition, the interconnect lines between the controller chip and each of the plurality of memory devices can also be tested. Finally, the present invention requires minimal setup time and performs a functional test of the memories in a very short period of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.