Structure and method for providing a reconfigurable emulation circuit without hold time violations
US5475830A · kind A · utility
127Cited by
24References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 1992 |
| Grant date | Dec 12, 1995 |
| Priority date | — |
| Expiry date | Jan 31, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a structure for implementing integrated circuit designs into a plurality of clocked and unclocked reprogrammable logic circuits. Software structures analyze the target logic circuit, form clusters, partition the integrated circuit design and implement the partitions into the clocked and unclocked reprogrammable logic circuits in order to prevent hold time violation artifacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.