MOS random access memory having array of trench type one-capacitor/one-transistor memory cells
US5477071A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 1995 |
| Grant date | Dec 19, 1995 |
| Priority date | — |
| Expiry date | Apr 7, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/395
Abstract
A random access memory device includes a semiconductive substrate having a surface in which a groove pattern is formed to provide a plurality of rows and columns of island portions. A plurality of trenches are formed in the island portions, which are provided with an array of memory cells arranged in rows and columns. Each of these memory cells consists of a capacitor and a metal oxide semiconductor (MOS) transistor which are stacked on each other in a corresponding one of the trenches. Parallel word lines are coupled to the rows of memory cells, and parallel bit lines are coupled to the columns of memory cells. An insulative layer is buried in each groove for causing adjacent ones of the island portions to be electrically isolated from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.